CLKGATE_DELAY=CLKGATE_DELAY_0, REFTOP_VBGADJ=REFTOP_VBGADJ_0, RTC_XTAL_SOURCE=RTC_XTAL_SOURCE_0, VID_PLL_PREDIV=VID_PLL_PREDIV_0, OSC_I=NOMINAL, REFTOP_SELFBIASOFF=REFTOP_SELFBIASOFF_0, CLKGATE_CTRL=ALLOW_AUTO_GATE, DISCON_HIGH_SNVS=DISCON_HIGH_SNVS_0, STOP_MODE_CONFIG=STOP_MODE_CONFIG_0
Miscellaneous Register 0
| REFTOP_PWD | Control bit to power-down the analog bandgap reference circuitry |
| REFTOP_SELFBIASOFF | Control bit to disable the self-bias circuit in the analog bandgap 0 (REFTOP_SELFBIASOFF_0): Uses coarse bias currents for startup 1 (REFTOP_SELFBIASOFF_1): Uses bandgap-based bias currents for best performance. |
| REFTOP_VBGADJ | Not related to oscillator. 0 (REFTOP_VBGADJ_0): Nominal VBG 1 (REFTOP_VBGADJ_1): VBG+0.78% 2 (REFTOP_VBGADJ_2): VBG+1.56% 3 (REFTOP_VBGADJ_3): VBG+2.34% 4 (REFTOP_VBGADJ_4): VBG-0.78% 5 (REFTOP_VBGADJ_5): VBG-1.56% 6 (REFTOP_VBGADJ_6): VBG-2.34% 7 (REFTOP_VBGADJ_7): VBG-3.12% |
| REFTOP_VBGUP | Status bit that signals the analog bandgap voltage is up and stable |
| STOP_MODE_CONFIG | Configure the analog behavior in stop mode.Not related to oscillator. 0 (STOP_MODE_CONFIG_0): All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; 1 (STOP_MODE_CONFIG_1): Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; 2 (STOP_MODE_CONFIG_2): XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. 3 (STOP_MODE_CONFIG_3): XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. |
| DISCON_HIGH_SNVS | This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. 0 (DISCON_HIGH_SNVS_0): Turn on the switch 1 (DISCON_HIGH_SNVS_1): Turn off the switch |
| OSC_I | This field determines the bias current in the 24MHz oscillator 0 (NOMINAL): Nominal 1 (MINUS_12_5_PERCENT): Decrease current by 12.5% 2 (MINUS_25_PERCENT): Decrease current by 25.0% 3 (MINUS_37_5_PERCENT): Decrease current by 37.5% |
| OSC_XTALOK | Status bit that signals that the output of the 24-MHz crystal oscillator is stable |
| OSC_XTALOK_EN | This bit enables the detector that signals when the 24MHz crystal oscillator is stable. |
| CLKGATE_CTRL | This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block 0 (ALLOW_AUTO_GATE): Allow the logic to automatically gate the clock when the XTAL is powered down. 1 (NO_AUTO_GATE): Prevent the logic from ever gating off the clock. |
| CLKGATE_DELAY | This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block 0 (CLKGATE_DELAY_0): 0.5ms 1 (CLKGATE_DELAY_1): 1.0ms 2 (CLKGATE_DELAY_2): 2.0ms 3 (CLKGATE_DELAY_3): 3.0ms 4 (CLKGATE_DELAY_4): 4.0ms 5 (CLKGATE_DELAY_5): 5.0ms 6 (CLKGATE_DELAY_6): 6.0ms 7 (CLKGATE_DELAY_7): 7.0ms |
| RTC_XTAL_SOURCE | This field indicates which chip source is being used for the rtc clock. 0 (RTC_XTAL_SOURCE_0): Internal ring oscillator 1 (RTC_XTAL_SOURCE_1): RTC_XTAL |
| XTAL_24M_PWD | This field powers down the 24M crystal oscillator if set true. |
| VID_PLL_PREDIV | Predivider for the source clock of the PLL’s. Not related to oscillator. 0 (VID_PLL_PREDIV_0): Divide by 1 1 (VID_PLL_PREDIV_1): Divide by 2 |